Chip layout design of a Josephson LSI circuit for examininghigh-speed operability by using a standard cell automatic placement androuting technique |
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| Authors: | Aoyagi M. Hamazaki Y. Nakagawa H. Kurosawa I. Maezawa M. Takada S. |
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| Affiliation: | Electrotech. Lab., Tsukuba; |
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| Abstract: | A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed |
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