Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration

This brief presents an adaptive-bandwidth (BW) phase-locked loop (PLL) that retains the optimal jitter performance over a wide frequency range via continuous background frequency calibration. The effective center frequency of the voltage-controlled oscillator (VCO) is calibrated by adjusting the feedforward division factor while a dual-PLL architecture hides the switching transients. As a result, the core ring oscillator only needs to operate over a narrow frequency range of 2 : 1 that is optimal for the jitter, supply sensitivity, and charge pump current mismatch over process, voltage, and temperature (PVT) conditions. The prototype PLL was fabricated in a 0.13-$muhbox{m}$ CMOS process, consumed 36 mW of power, and occupied $1.1 times 0.46 hbox{mm}^{2}$ of area. The measured root-mean-square (RMS) tracking jitter was less than 0.2% of the reference clock period for the wide range of output frequency (2 MHz–1 GHz) and multiplication factor $(2^{0 - 9})$, which supports that the PLL BW scales adaptively with the reference frequency. Compared to a PLL without frequency calibration, the proposed PLL demonstrated the jitter reduction up to 80%.