高速32位伪随机数发生器电路设计

文章提出了一种实现32位伪随机发生器电路设计方案。该方案的关键是对产生伪随机数所需要的乘法器和模2n－1加法器的设计。针对所采用的伪随机数迭代函数的特殊性，提出了特定的32位×16位乘法器以及模231－1加法器实现方案，使电路的速度得以提高，规模得以减小。整个电路设计采用VHDL语言描述，并通过了逻辑仿真验证。文章同时介绍了一般乘法器以及并行前缀模2n－1加法器的设计原理。

The Circuit Design of High Speed 32-bits Pseudorandom Number Generator

： A new circuit design scheme is proposed in the paper，which implements pseudorandom number generator．The key of this scheme is the design of multiplier and modulo 2n－1 adder needed by pseudorandom number generator．In allusion to the particularity of the iterative function adopted，we proposed the scheme for specifical multiplier of 32－bit×16－bit and modulo 2n－1 adder．The scheme improves speed of circuit and decreases delay．The design module is described in VHDL，and has passed the logic verification．Simultaneously，the paper introduce principles of designing commonly multiplier and parallel－prefix modulo 2n－1 adder．