基于FPGA的ARINC659总线同步机制的研究与实现

ARINC659总线是综合化模块化航空电子中现场可更换模块(LRM)之间数据的传送标准总线，多重冗余结构和时间窗口触发的帧收发运行控制机制是 ARINC659总线的主要优点，该总线控制器实现的一个难点在于对其同步机制的实现。本文介绍了 ARINC659总线协议的基本内容，着重研究了该总线协议的同步机制，并在 Libero 平台下使用 A3P 系列 FPGA 用 verilog 语言对总线控制器进行编程，并用在线调试工具 identify 进行采样。最终测试结果表明，总线控制器同步系统工作正常、稳定，符合协议要求。

Research and implementation of the synchronization mechanism of ARINC659 BUS based on FPGA

ARINC659 bus is a standard bus of data transfer between LRMs in Avionics which can be Integerated and modulared.The strong point of ARINC659 bus are the multiple redundant structure and the TDPA method used in Frame transceiver.One difficulty of ARINC659 bus is implementing its synchronization mechanism.This paper introduced the basic content of ARINC659 bus espscially the synchronization mechanism of ARINC659 bus .Using A3P FPGA and verilog to describe the synchronization mechanism of ARINC659 bus under Libero platform and sample the singal by online debugging tool called identify.The final test results show that the system is normal and stable which is accord with the requirements of the protocol.