A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS |
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| Authors: | Foley D.J. Flynn M.P. |
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| Affiliation: | Parthus Technol., Dublin; |
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| Abstract: | An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 1013 for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-μm digital CMOS, occupies 2 mm2, and dissipates 400 mW from a 3.3-V supply |
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