| 2831／2位BCCD模拟延迟线的研制 |
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| 引用本文： | 胡世忠 贾晋冀. 2831／2位BCCD模拟延迟线的研制[J]. 半导体光电, 1990, 11(3): 210-215 |
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| 作者姓名： | 胡世忠 贾晋冀 |
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| 作者单位： | 重庆光电技术研究所，重庆光电技术研究所 重庆市永川 632163，重庆市永川 632163 |
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| 摘 要： | 采用四相埋沟结沟制作了器件,其转移效率超过99.99%,时钟频率超过10MHz。本文阐述了器件原理、结构和工艺以及提高器件参数的重要途径。
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| 关 键 词： | BCCD 模拟 延迟线 结构 工艺 |
Research & Development of 283~(1/2) Bit BCCD Analog Delay Lines |
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| Hu Shizhong Jia Jinji Chongqing Optoelectronics Research institute Yongehuan,Chongqing. Research & Development of 283~(1/2) Bit BCCD Analog Delay Lines[J]. Semiconductor Optoelectronics, 1990, 11(3): 210-215 |
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| Authors: | Hu Shizhong Jia Jinji Chongqing Optoelectronics Research institute Yongehuan Chongqing |
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| Affiliation: | Hu Shizhong Jia Jinji Chongqing Optoelectronics Research institute Yongehuan,Chongqing 632163 |
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| Abstract: | A 283(1/2) bit BCCD analog delay line whose transfer efficiency is over 99.99% and clock frequency over 10 MHz has been fabricated with four-phase buried struclute.The principle,configuration and technology of the device are des- cribed as weIl as an important approach to the impmovement of the device parameters. |
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| Keywords: | Analog Delay Line Configuration and Process |
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