一种带分数延时功能的符号同步环路的设计与实现

模拟下变频或基于多相滤波的数字正交变换都可能会在IQ路之间引入一个固定的分数倍采样点的延时，本文提出一种分数延时校正和符号定时同步相结合的方案，使两种误差在同一个环路中得到解决，符号定时同步环路采用Gardner时钟误差鉴相算法和拉格朗日内插算法，方案在1024QAM解调系统中验证成功。

Design and Implementation of a Fractional-delay Function for Symbol Synchronization Loop

Analog down conversion or digital orthogonal transform based on polyphase filter may be introduce a fixed fractional-delay of sampling points between IQ channel, this paper presents a scheme that combining the fractional-delay correction and symbol timing synchronization, the two types of errors are resolved in the same loop, Symbol timing synchronization loop using Gardner algorithm detecting timing error and Lagrange algorithm interpolating, The scheme was proved to be successful in 1024QAM demodulation system.