片内二级Cache的静态功耗优化技术研究

随着集成电路制造工艺进入超深亚微米阶段,静态功耗在微处理器总功耗中所占的比例越来越大,尤其是片上二级Cache。在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化静态功耗成为业界研究的热点。本文提出了一种ADSR算法,在保证处理器性能不受影响的前提下,可以大幅降低二级Cache的静态功耗。

The Leakage Power Optimization in On-Chip L2 Caches

The static power exceed the dynamic power in microprocessors as the feature size shrinks,especially for on-chip L2 caches.Beside developing low leakage technologies and circuits,how to control the static power at the architectural level is worth being studied.In this paper,an ADSR algorithm is proposed to optimize the L2 cache's static power dissipation.The SPEC CPU2000 simulation results show that,with negligible performance loss,ADSR can aggressively decrease the static power dissipation of on-chip L2 caches.