The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon

An abnormal gate oxide failure was found in DRAM using deep submicron technology. Contrary to the general dielectric extrinsic breakdown, the degradation of gate oxide integrity was shown only in the gate lines of a small dimension, not in those of a large dimension. This abnormal oxide breakdown is due to the voids in the polycrystalline silicon, which are at the center of gate line with a small dimension. These voids are formed by both chemical potential difference and stress enhanced diffusion of polycrystalline silicon. The suppression method of these voids using sufficient source of polycrystalline silicon is proposed.