基于相位合成的时钟50%占空比调节电路设计

本文介绍了采用纯数字相位合成法设计的高性能时钟50%占空比调节电路PB-DCC(Phase-Blending Duty-Cycle Corrector).相比于传统的占空比调节方式,此电路通过采用SMD(Synchronous Mirror Delay)技术具有较强的抗PVT(Process,Voltage and Temperature)变化的能力,输出时钟和原时钟完全同步和较快的调节速度等特点.经0.13μm CMOS工艺版图实现后HSPICE模拟表明,该占空比调节电路对占空比在10%~90%范围内的400MHz时钟能在4个周期内完成调节,输出时钟占空比为48%~52%.

Design of 50% Duty-Cycle Correction Based on Phase-Blending

A high performance 50% phase blending duty-cycle corrector(PB-DCC),designed with a purely digital phase-blending technique,is presented in this paper.The novel features of the proposed DCC include a higher reliability against process,voltage and temperature(PVT) variation due to the use of the synchronous mirror delay(SMD) technique,no-skew output clock,and much faster duty-cycle correction speed compared to conventional DCC's.When designed with a 0.13 μ m CMOS technology,the HSPICE simulation indicates that the acceptable duty-cycle of input signal ranges from 10% to 90% when the clock frequency is 400MHz and the correction operation spends only 4 clock cycles with output duty-cycle varying from 48% to 52%.