Application of Scanning Capacitance Microscopy on SOI device with wafer edge low yield pattern

As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product was the key component for this kind of application. SOI (Silicon-On-Insulator) wafer process is one of the advanced and important branches of the semiconductor manufacturing process. Its intrinsic advantage, low leakage and lower power consuming make it very suitable for personal communication device and IOT which match well with the application requirement. As is well known the SOI wafer is different form the normal bulk silicon wafer. The active sits on the silicon oxide insulator, which makes the final device separate from the substrate. Basically, all of the devices are floating on a nonconductive oxide layer. It comes with many challenges for process and analysis as compared with the conventional bulk silicon process.The most conventional analysis method is not applicable in the SOI device such as the PVC (passive voltage contrast) and current image methodology which are a very powerful and important in the failure analysis.In this paper, scanning capacitance is successfully used as the substitution of the PVC method. The SCM (Scanning Capacitance Microscopy) is a complicated process. Since all of the abnormality or physical change will affect the measured capacitance, then the capacitance signal will theoretically has many information with itself, including open, short and leakage. Through the detailed study, the contact level top-down SCM was successfully applied on the SOI unit. By proper setting of SCM bias condition, it can not only visualize the possible leaky location but also can reveal the possible path. Further nanoprobing and TEM (Transmission Electron Microscopy) have confirmed the SCM analysis.