Evaluating the material properties of underfill for a reliable 3D TSV integration package using numerical analysis |
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| Affiliation: | 1. School of Mechanical Engineering, Chonnam National University, 77 Yongbong-ro, Buk-gu, Gwangju 61186, Republic of Korea;2. Convergence Components & Materials Research Laboratory, Electronics and Telecommunications Research Institute, 218 Gajeong-ro, Yuseong-gu, Daejeon 34129, Republic of Korea;1. University of Paris, LTIE-GTE EA 4415, 50, rue de Sèvres, F-92410 Ville d''Avray, France;2. Polytechnic Institute of Coimbra, ISEC, DEM, Rua Pedro Nunes, Quinta da Nora, 3030-199 Coimbra, Portugal;3. University of the Basque Country, ENEDI Research Group, Plaza Europa 1, E-20018 San Sebastián, Spain;4. University of Bath, Department of Architecture and Civil Engineering, Claverton Down, Bath BA2 7AY, UK;1. Erich Schmid Institute of Materials Science, Austrian Academy of Sciences, Jahnstrasse 12, Leoben, Austria;2. Vienna University of Technology, Institute of Chemical Technologies and Analytics, Vienna, Austria;3. Christian Doppler Laboratory for Lifetime and Reliability of Interfaces in Complex Multi-Material Electronics, CTA, TU Wien, Vienna, Austria;4. Infineon Technologies Austria AG, Villach, Austria;5. Infineon Technologies Germany AG, Regensburg, Germany;6. Kompetenzzentrum Automobil- und Industrie-Elektronik GmbH, Villach, Austria |
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| Abstract: | The effects of the material properties of the underfill layer on thermal stress and deformation in 3D through silicon via (TSV) integration packages were evaluated through numerical analysis. Sample TSV packages with underfill composed of different silica volume ratios were fabricated. The sample packages were used to measure thermal deformation using a Moiré interferometer. Also, a cross-section from these samples was used for 2D finite element modeling and numerical analysis to obtain its thermal deformation. The experimental and numerical results were compared to confirm the suitability of the numerical technique in this research. A four-chip-stacked TSV integration package, which includes underfill layers of four different silica volume ratios, was proposed and designed. The diagonal part of the TSV integration packages were three dimensionally modeled and adopted for numerical analysis. Among the underfill with different silica volume ratios in the designed packages, a silica volume ratio of around 20% shows the best performance for a reliable flip chip bonding process, effectively minimizing thermal stress and deformation in the package. |
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