Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection |
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| Affiliation: | 1. Department of Materials Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran;2. Delft University of Technology, EEMCS Faculty, Delft, The Netherlands;1. Federal University of Minas Gerais, Belo Horizonte, Brazil;2. Univ. Grenoble Alpes, CNRS, TIMA, Grenoble, France;1. Department of Manufacturing and Materials Engineering, University of Campinas, UNICAMP, 13083-860 Campinas, SP, Brazil;2. Federal Institute of Education, Science and Technology of Pará, IFPA, 66093-020 Belém, PA, Brazil;1. State Key Lab of Electronic Thin Films & Integrated Devices, University of Electronic Science & Technology of China, Chengdu, China;2. Institute of Biomedical Engineering, Chinese Academy of Medical Science and Peking Union Medical College, 300192 Tianjin, China;3. Design center, Avic Beijing Keeven Aviation Instrument CO., LTD, China Aviation Industry Corporation, Beijing, China;1. Department of Electrical Engineering, National Taiwan Normal University, Taiwan;2. Institute of Electronics, National Chiao Tung University, Taiwan |
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| Abstract: | The reliability of microprocessors is a big concern in space environments, where they are exposed to cosmic radiation. This radiation can produce Single Event Upsets (SEUs). Some of these microprocessors, often called soft processors, are implemented on SRAM-based FPGAs instead of being manufactured as an ASIC. Fault injection campaigns are needed in order to estimate the soft processor reliability in this harsh environment. This work, characterizes a new RISC soft-core, called lowRISC, based on the RISC-V ISA. Ten tests have been carried out to characterize the SEU sensitivity of lowRISC. Also, we have performed a comparison among lowRISC and other microprocessors, concluding that their sensitivities are all in the same range. |
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