Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology |
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| Affiliation: | 1. College of Computer, National University of Defense Technology, Changsha 410073, China;2. Runtronic Co., Ltd., Changsha 410073, China;3. School of Software, Harbin Institute of Technology, Harbin 150001, China;1. Department of Instrumentation and Applied Physics, Indian Institute of Science, Bangalore 560012, India;2. Department of Materials Engineering, Indian Institute of Science, Bangalore 560012, India;1. Robert Bosch GmbH, Reliability Modeling and System Optimization (AE/EDT3), Reutlingen 72703, Germany;2. Mechanical Engineering Department, University of Maryland College Park, MD 20742, USA;3. Fraunhofer-Institut für Betriebsfestigkeit und Systemzuverlässigkeit LBF, Darmstadt 64289, Germany;1. Department of Electronics Technology, Budapest University of Technology and Economics, Budapest, Hungary;2. Czech Technical University in Prague, Faculty of Electrical Engineering, Department of Electrotechnology, Technická 2, Prague 6 166 27, Czech Republic;1. Institute of Electronics, Technical University of ?ód?, ul. Wolczańska 211-215, 90-924 ?ód?, Poland;2. Department of Electronics and Information Systems, Ghent University, Sint Pietersnieuwstraat 41, 9000 Ghent, Belgium;3. Department of Electrical and Computer Engineers, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece |
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| Abstract: | We report single-event transient (SET) responses of an on-chip linear voltage regulator in 130 nm commercial standard CMOS technology by heavy ion experiments at first. Responses can be distinguished by the load current. When the light load current was applied, the negative SET on the output of the regulator larger than 200 mV was not observed, while the positive SETs that are larger than 400 mV and last for about 200 ns were observed. By comparison, when the heavy load current was applied, both positive and negative SETs that are larger than 400 mV and last for several hundred ns were observed. Next, the mechanism behind the phenomenon is analysed and then verified by the post-layout SPICE circuit simulation. It is demonstrated that the input voltage, load current and the load capacitance are key elements in determining the severity of SET. Finally, the most sensitive node is located by analysis and SPICE circuit simulation, which lies in the output of the amplifier inside of the bandgap reference (BGR). This result is a primary consideration in the development of the hardening technique. |
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