Reliability of 100 nm AlGaN/GaN HEMTs for mm-wave applications |
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| Affiliation: | 1. Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, D-79108 Freiburg, Germany;2. Fraunhofer Institute of Microstructure of Materials and Systems, , Walter-Hülse-Strasse 1, D-06120 Halle, Germany;1. Deggendorf Institute of Technology, Dieter-Görlitz-Platz 1, 94469 Deggendorf, Germany;2. Universitat Autònoma de Barcelona (UAB), 08193 Bellaterra, Barcelona, Spain;1. Fraunhofer Institut für Zuverlässigkeit und Mikrointergation, 13355 Berlin, Germany;2. Forschungsschwerpunkt Technologien der Mikroperipherik, Technische Universität Berlin, 13355 Berlin, Germany;1. Engineering Product Development Pillar, Singapore University of Technology and Design, 487372, Singapore;2. State Key Laboratory of Modern Optical Instrumentation, College of Optical Science and Engineering, Zhejiang University, Hangzhou 310027, China;1. LAAS-CNRS and Université de Toulouse, Université Paul Sabatier, 31031 Toulouse, France;2. United Monolithic Semiconductors, Villebon-sur Yvette 91140, France;3. DGA MI, Rennes 35998, France;4. SERMA Technologies MINATEC BHT, Grenoble 38040, France;5. Biophy Research, Fuveau 13710, France;6. CNES, Quality Assurance Directorate Department, Toulouse 31400, France |
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| Abstract: | The effect of gate metallization and gate shape on the reliability and RF performance of 100 nm AlGaN/GaN HEMTs on SiC substrate for mm-wave applications has been investigated under on-state DC-stress tests. By replacing the gate metallization from NiPtAu to PtAu the median time to failure at Tch = 209 °C can be improved from 10 h to more than 1000 h. Replacing the PtAu T-gate by a spacer gate further reduces the degradation rate under on-state stress, but decreases the current-gain cut-off frequency from 75 GHz to 50 GHz. Physical failure analysis using electroluminescence and TEM cross-section revealed pit and Ni void formation at the gate foot as the main degradation mechanisms of devices with NiPtAu T-gate. High resolution EDX mapping of stressed devices indicates that the formation of pits is caused by a local aluminium oxidation process. Simulation of the stress induced changes of the input characteristics of devices with NiPtAu gate further proves the formation of pits and Ni voids. |
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