Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments |
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| Affiliation: | 1. Department of Electrical Engineering, COMSATS Institute of Information Technology, Islamabad, Pakistan;2. Skobeltsyn Institute of Nuclear Physics, Moscow State University, Moscow, Russia;3. Department of Electronics Engineering, UFMG, Belo Horizonte, Brazil;4. University of Lahore, Islamabad Campus, Islamabad, Pakistan;5. Department of Electrical and Computers Engineering, University of Auckland, New Zealand;6. China Academy of Space Technology (CAST), Beijing, China;7. Department of Physics, International Islamic University, Islamabad, Pakistan;1. Department of Manufacturing and Materials Engineering, University of Campinas, UNICAMP, 13083-860 Campinas, SP, Brazil;2. Federal Institute of Education, Science and Technology of Pará, IFPA, 66093-020 Belém, PA, Brazil;1. Department of Electrical Engineering, National Taiwan Normal University, Taiwan;2. Institute of Electronics, National Chiao Tung University, Taiwan;1. State Key Lab of Electronic Thin Films & Integrated Devices, University of Electronic Science & Technology of China, Chengdu, China;2. Institute of Biomedical Engineering, Chinese Academy of Medical Science and Peking Union Medical College, 300192 Tianjin, China;3. Design center, Avic Beijing Keeven Aviation Instrument CO., LTD, China Aviation Industry Corporation, Beijing, China;1. Mechanical Engineering Department, University of Maryland College Park, MD 20742, USA;2. Mechanical and Aerospace Engineering, Seoul National University, Republic of Korea;3. Package Development Team, Semiconductor R&D Center, Samsung Electronics, Republic of Korea |
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| Abstract: | The degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software. |
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