Gate oxide integrity dependence on substrate characteristics and SiO2 thickness |
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Affiliation: | 1. National Scientific and Technical Research Council (CONICET), Av. Rivadavia 1917, Buenos Aires, Argentina;2. Department of Electronic Engineering, National Technological University (UTN), Medrano 951, Buenos Aires, Argentina;3. GAIANN, Comision Nacional de Energia Atomica, Gral. Paz 1499 (1650), Buenos Aires, Argentina;4. Istituto per la Microelettronica e Microsistemi (IMM) Consiglio Nazionale delle Ricerche (CNR), Zona Industriale, Ottava Strada, 5, 95121 Catania, Italy;5. Department of Materials Science and Engineering, Technion — Israel Institute of Technology, 32000 Haifa, Israel |
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Abstract: | Gate oxide integrity (GOI) has been investigated for a wide range of oxide thicknesses, from 5 to 50 nm. Silicon substrates containing voids of number densities along with defect-free (perfect) polished and epitaxial wafers were tested. Oxide reliability was monitored by linear ramped field tests at variable ramp rate and by constant current and field tests using a doped polysilicon gate as the cathode. The field and time parameters characterizing the distributions of each breakdown mode have been extracted by Weibull analysis. In general, more than one mode of breakdown is found in a given sampled substrate type. The average field of the breakdown shifts to higher fields with decreasing oxide thickness. In the void-related mode, a constant countable number of defects for a given substrate type are “activated” at sufficiently high fields independent of oxide thickness. Void-free epi and “perfect” substrates show a single, non-intrinsic breakdown mode. This mode is also found in the void containing materials in the part of their distribution, unaffected by voids. |
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