67×67位乘法器的改进四阶Booth算法实现

针对67×67位乘法器,提出并实现新型的设计方法.先提出改进的四阶Booth算法,对乘数编码,以减少部分积的数目,提高压缩速度和减少面积,再研究优化和分配方法,对部分积和进位信号以及一个134位的补偿向量进行优化分配,并对部分积压缩,最后研究K-S加法器的改进方法,求和以实现134位乘积.采用TSMC的0.18 μm工艺库,Synopsys的Design compiler工具和Altera的Quautus4.2工具分析结果表明,基于本文方法实现的电路比DesignWare自带的乘法器实现的电路相比,性能总体占优.

Design of a 67×67 bits Multiplier Employed Modified Booth4 Algorithm

It is proposed that a novel method for the design of 67×67 bits multiplier.First,a modified Booth4 algorithm is presented,which reduces the number of partial products,increases the compressing speed,and reduces the area by encoding the multipliers.After,research of optimizing and assigning to the carries generated by partial products and a 134 bits compensatory pattern,partial products are compressed by 4-2 and 3-2 compressors.At last,a modified 134 bits K-S adder is presented and employed to ge...