A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-inself-test |
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| Authors: | Bonges H.A. III Adams R.D. Allen A.J. Flaker R. Gray K.S. Hedberg E.L. Holman W.T. Lattimore G.M. Lavalette D.A. Nguyen K.Y.T. Roberts A.L. |
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| Affiliation: | IBM Gen. Technol. Div., Essex Junction, VT; |
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| Abstract: | An experimental 576 K BiCMOS emitter-coupled-logic (ECL)-compatible SRAM that achieves 3.5-ns access and cycle is discussed. The SRAM is fully self-testable using less than 1 K on-chip logic gates to assist characterization, wafer testing, and package testing. The I/O is also transistor-transistor-logic (TTL) programmable with the first-metal mask |
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