基于门控时钟的寄存器传输级功耗优化

随着深亚微米技术的发展,功耗已经成为现代超大规模集成电路设计中的一个主要设计约束.本文在设计多点控制协议MPCP模块中,采用插入门控时钟这一技术以降低芯片功耗.针对插入门控寄存器造成测试很难控制这个问题,采取在锁存器的前后加入控制点的方法,解决了由于插入门控时钟而对可测性造成的影响.最后,使用SMIC的0.25um CMOS工艺,并用Synopsys的power complier进行功耗优化,达到了很好的效果.

Low Power Design in the MPCP Module

With the development of the deep sub-micron technology,the power consumption of the integrated circuit (IC) has become a dominant design constraint in modern VLSI design. In this paper, the methodology of clock gating is presented to decrease the power consumption. Based on the design of MPCP module, aiming at the issue that clock-gating register is difficult to control during the test, inserting control point before or after the clock-gating latch is used to solve the negative effect of clock gating. Finally, implementing the power optimization by means of Power Compiler, a satisfying result is reached using the SMIC 0.25 um CMOS process.