基于部分簇能量互补逻辑的MRF电路设计

功耗是电路设计的关键性问题之一，低功耗下的稳定性问题逐渐成为电路设计的热点和挑战，基于马尔科夫随机场（MRF）的低功耗设计从能量的角度出发有效地解决了电路的容错问题，但是其单逻辑的单元结构面积和复杂度制约了该技术在大规模集成电路的应用。该文提出了一种基于部分簇能量的MRF电路设计方法（PMRF），并结合互补逻辑的特点来实现多逻辑结构，面积共享的同时一方面补偿由于部分簇能量带来的性能损失，一方面化简马氏随机场电路设计在较大规模电路设计中的面积和复杂度瓶颈问题。对比传统MRF电路设计，该文用PMRF方法设计了超前进位加法器结构，在低功耗仿真中具有20%的性能提升，并在65 nm TSMC版图实现后取得29%的面积节约和86%的功耗节约。

MRF Circuits Design with Complementary Partial Clique Energy Method

Power consumption is a key issue in digital circuit design. The reliability of circuits becomes one of main challenges for low supply voltage design. Markov random field (MRF) circuits, which are the probabilistic-based approaches with energy based point of view, can achieve high noise immunity in ultra-low supply. However the traditional MRF elements have complex structures which become a stringent limitation factor for the application of MRF-based circuits in VLSI design. In this paper, we present a partial MRF (PMRF) clique energy design method for multi-logic elements, which can be referred to complementary PMRF pair. The proposed structure compensates the performance loss and achieves the area and complexity reduction. A full carry-look-ahead adder is implemented by using our proposed PMRF-pairs on the 65 nm TSMC CMOS technology. The measurement results show that the PMRF-pairs design can achieve higher fault-tolerance while occupying 29% area-saving, 86% energy-saving and 20% performance improvement compared with the complete MRF design.