基于Zynq平台PCIE高速数据接口的设计与实现 |
| |
引用本文: | 杨亚涛,张松涛,李子臣,张明舵,曹广灿. 基于Zynq平台PCIE高速数据接口的设计与实现[J]. 电子科技大学学报(自然科学版), 2017, 46(3): 522-528. DOI: 10.3969/j.issn.1001-0548.2017.03.008 |
| |
作者姓名: | 杨亚涛 张松涛 李子臣 张明舵 曹广灿 |
| |
作者单位: | 1.北京电子科技学院通信工程系 北京 丰台区 100070 |
| |
基金项目: | 国家自然科学基金61370188中央高校基本科研业务费专项资金2017XK01 |
| |
摘 要: | 为有效利用PCIE接口的优异传输性能,便于外设与主机进行高速通信,该文基于Xilinx公司Zynq系列芯片,设计实现了多通道、高速度的PCIE接口。利用Zynq-7000系列芯片的FPGA+ARM架构,在PCIE2.0硬核的基础上设计了DMA硬核控制器、设备驱动和应用程序。经测试,在PCIE×1通道和单逻辑通道时,传输速度能达到3.36 Gbps,相比现有设计提升近20%。方案设计完备,具有较强扩展性,为设计基于PCIE接口的外接设备提供了重要参考,具有广阔应用前景。
|
关 键 词: | ARM DMA FPGA 硬件设计 PCIE |
收稿时间: | 2016-01-24 |
Design and Implementation for High Speed Data Transfer Interface of PCI Express Based on Zynq Platform |
| |
Affiliation: | 1.Department of Communication Engineering, Beijing Electronic Science & Technology Fengtai Beijing 1000702.Office of Educational Administration, Beijing Graphic Communication Daxin Beijing 102600 |
| |
Abstract: | In order to use the excellent transmission performance of peripheral component interconnect express (PCIE) interface to carry out high-speed communication between peripherals and the host effectively, a multi-channel and high-speed PCIE interface scheme is designed based on Zynq family chip of Xilinx. The DMA hardcore controller, device driver and application program are designed on the basis of PCI express 2.0 hardcore using the FPGA+ARM architecture of Zynq-7000 platform. Test results show that the transfer rate in our project almost can reach 3.3 Gbps in PCIE×1 lane and single logical channel, which increases about 20% compared with the traditional existing designs. Our scheme owns higher expansibility and wide application prospect, it is an important design reference for external equipment and PCIE interface. |
| |
Keywords: | |
|
| 点击此处可从《电子科技大学学报(自然科学版)》浏览原始摘要信息 |
|
点击此处可从《电子科技大学学报(自然科学版)》下载全文 |
|