| 合成孔径雷达定时器的FPGA实现 |
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| 引用本文： | 高俊峰,李早社,吕磊,杨汝良.合成孔径雷达定时器的FPGA实现[J].现代雷达,2006,28(11):33-35. |
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| 作者姓名： | 高俊峰 李早社 吕磊 杨汝良 |
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| 作者单位： | 中国科学院电子学研究所,北京,100080 |
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| 摘 要： | 给出了一种采用FPGA实现合成孔径雷达定时器的设计方案，通过合理的时钟设计，使全局时钟的畸变达到最小，保证得到高质量同步的全局时钟。同时对工作时钟采用二的幂次方分频后作为脉冲宽度和延时的调整时钟，从向保证了控制精度。实验证明，该定时器具有输出脉冲抖动小，脉冲宽度和延时控制精确，集成度高，可靠性好的优点。
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| 关 键 词： | 合成孔径雷达 定时器 可编程门阵列 |
| 收稿时间： | 2006-06-14 |
| 修稿时间： | 2006-09-22 |
FPGA Implementation of Timer for Synthetic Aperture Radar |
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| GAO Jun-feng,LI Zao-she,LV Lei,YANG Ru-liang.FPGA Implementation of Timer for Synthetic Aperture Radar[J].Modern Radar,2006,28(11):33-35. |
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| Authors: | GAO Jun-feng LI Zao-she LV Lei YANG Ru-liang |
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| Affiliation: | Institute of Electronics, Chinese Academy of Sciences, Beijing 100080, China |
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| Abstract: | In this paper, a scheme of radar timer based on FPGA for SAR is given. The reasonable clock design minimizes the skew of Global Clock and gets accurate synchronous Global Clock. Meanwhile, the width and delay of output pulse is adjusted by the work clock whose frequency is divided by the designated power of 2. It has been proven that this radar timer has the merits of little pulse jitter, flexibility, integration and reliability. |
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| Keywords: | synthetic aperture radar timer FPGA |
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