3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay |
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Authors: | Jagannathan B Meghelli M Chan K Jae-Sung Rieh Schonenberg K Ahlgren D Subbanna S Freeman G |
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Affiliation: | IBM Microelectron. Semicond. R&D Center, Hopewell Junction, NY, USA; |
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Abstract: | We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f/sub MAX/ (338 GHz) and a low f/sub T/ (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f/sub T/ and f/sub MAX/, a simple figure of merit proportional to /spl radic/f/sub T//R/sub B/C/sub CB/ with R/sub B/ and C/sub CB/ extracted from S-parameter measurement is best correlated to the minimum gate delay. |
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