Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Most well established IR-beam based failure analysis techniques and also conventional circuit edit procedures are facing severe challenges resulting from the aggressive downscaling of today’s IC technology. To allow for alternative strategies, novel CE and functional chip analysis techniques have been developed, all being based on backside FIB processing. Additionally, in depth characterization of FIB induced device alterations has shown that a >20% speed gain can be achieved with the proposed FIB thinning procedure. In contrast to all known techniques, this offers trimming of chip internal timing conditions on fully functional samples without being bound to pre-planned fuses or varactors. Based on various experimental results and physical device simulations, this paper briefly reviews the necessary FIB process for which the main focus lies on the FIB induced device alteration. Finally, the novel CE and analysis techniques will be discussed regarding their fields of application, benefits compared to established techniques and theoretical limitations.