Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology |
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Authors: | Park Kun-Sik Baik Kyu-Ha Kim Dong-Pyo Woo Jong-Chang No Kwang-Soo Lee Kijun Do Lee-Mi |
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Affiliation: | RFID/USN Research Department, Electronics and Telecommunications Research Institute, 138 Gajeongno, Yuseong-gu, Daejeon 305-700, Korea. |
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Abstract: | In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography. |
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