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弹载雷达信号处理SoC的设计与实现
引用本文:闵俊红,苏涛,郝珊珊. 弹载雷达信号处理SoC的设计与实现[J]. 空军雷达学院学报, 2013, 0(1): 1-5,10
作者姓名:闵俊红  苏涛  郝珊珊
作者单位:西安电子科技大学雷达信号处理国家重点实验室,西安710071
摘    要:为满足系统实时性要求,给出了一种弹载雷达信号处理系统的可编程SoC设计方案.它以SoC技术为基础,将雷达信号处理所需的专用功能模块尽可能地集成到一块芯片中,提高了芯片的通用性.将A/D采样、数字下变频、脉冲压缩、动目标检测、求模和恒虚警等功能模块集成到一片内嵌CPU硬核的FPGA芯片上进行测试验证,同时通过性能改善策略,提高了片上系统性能,满足了信号处理实时性要求.测试分析表明:该芯片具有快速的处理能力、较大的数据存储容量以及功耗较小的优点,且芯片中各模块间具有很高的通信速度.

关 键 词:弹载雷达  可编程SoC  实时信号处理  FPGA  单芯片集成

Design of Missile-borne Radar Signal Processor SoC and Its Implementation
MIN Jun-hong,SU Tao,HAO Shan-shan. Design of Missile-borne Radar Signal Processor SoC and Its Implementation[J]. Journal of Air Force Radar Academy, 2013, 0(1): 1-5,10
Authors:MIN Jun-hong  SU Tao  HAO Shan-shan
Affiliation:(National Laboratory of Radar Signal Processing, Xidian University, Xi'an 710071, China)
Abstract:In order to meet the demand of system real-time, this paper designs a programmable SoC scheme of missile-borne radar signal processing system, where, by employing the SoC technique, the specific application modules for radar signal processing are integrated in a single chip as far as possible, thus improving its versatility. In the scheme, A/D sampling, DDC, PC, MTD, CFAR and other functional modules are integrated into a FPGA chip that has an embedded CPU hardcore, on which the testing and checking are performed. Meanwhile, by taking the performance improving strategy, the on-chip system performances are improved and the real-time demand for signal processing is met. Test analysis shows that this proposed chip has advantages of fast-processing capability, larger data storage capacity and less power consumption as well as super communication rate between modules in the chip.
Keywords:missile-borne radar  programmable SoC  real-time signal processing  FPGA  single-chip integration
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