基于FPGA的高速数据采集系统设计

设计了一种以FPGA为主要控制芯片并通过串口与PC机进行数据通信的高速数据采集系统。FPGA内各个逻辑模块利用Verilog HDL语言进行设计,通过各功能模块分别实现高速模数转换芯片控制、数据采集处理以及与PC机之间的数据通信。系统发挥FPGA的并行数据处理能力,较传统以DSP和单片机为主要处理芯片的数据采集系统更能满足高速度、高稳定性、高实时性等要求。

Design of high-speed data acquisition system based on FPGA

We design a high-speed data acquisition system that uses FPGA as the main control chip, and it realizes the data communication with the PC through serial port . Each of these logic modules in FPGA is designed with Verilog HDL. By these various functional modules the system achieves high-speed analog-to-digital conversion chip control, data acquisition and processing and the communication with PC. With the use of parallel data processing ability of FPGA, compared with the traditional DSP and single-chip microcomputer as the main processing chip data acquisition system, this system can meet the high speed, high stability, high real-time requirements.