40nm节点高深宽比接触孔刻蚀电性能稳定性改善

随着工艺节点减小,对高深宽比接触孔形貌和关键尺寸的精准控制变得愈加困难。基于40 nm逻辑器件量产数据,研究了高深宽比接触孔刻蚀工艺参数和刻蚀设备内部耗材的磨损对器件电性能稳定性的影响,并提出了工艺改进方案。通过减小SiO_2厚度,减小接触孔深宽比,从而改善孔内聚合物在孔底部沉积的问题;通过优化刻蚀工艺参数提高SiN/SiO_2刻蚀选择比,保持刻蚀后SiO_2的厚度与改进前工艺相同。测试结果表明,工艺改进后接触孔底部关键尺寸稳定性提升36%,接触电阻稳定性提升20%。通过工艺改进提高了电参数稳定性,对40 nm工艺节点逻辑器件产品良率提升起到了关键作用。

Electric Stability Improvement of High Aspect Ratio Contact Hole Etching in 40 nm Process Node

As the process nodes decrease,it becomes more difficult to control the morphology and critical dimensions of the high aspect ratio contact hole accurately.Based on the mass production data of the 40 nm logic devices,the influences of etching process parameters of high aspect ratio contact holes and the consumable parts of the etching equipment on the stability of the device electrical parameters were studied and a process improvement scheme was proposed.,The polymer residue in the bottom of the holes was improved by reducing the thickness of SiO2 and the aspect ratio of the contact holes.The thickness of SiO2 after etching was the same as the original process by optimizing process parameters to improve the selection ratio of SiN/SiO2 etching.The test results show that the stability of the critical dimension of the bottom of the contact holes increases by 36% and the stability of the contact resistance increases by 20%.The stability of the electrical parameters is improved by improving the existing process,which plays a key role in improving the yield of 40 nm process node logic devices.