A new hardware-efficient digital sinusoidal oscillator with low- and uniform-frequency spacing

In this paper, a new low-frequency digital sinusoidal oscillator with uniform-frequency spacing is proposed, and its performance is evaluated. The proposed oscillator structure, P, requires a single, short word-length multiplier for its hardware implementation. For the same frequency range, the single multiplier utilized can be implemented using an 8-bit word length, assuming that the multipliers in the previously reported oscillators, such as the multiple-output direct form digital oscillator and its modified versions, are implemented using 16 bits. The saving in multiplier word length results in a reduction in the silicon area and power dissipation. The proposed oscillator structure utilizes a multiple-output direct form digital oscillator with a single, short word-length multiplier in addition to a very simple switching and sign changing operation. The proposed oscillator structure is capable of generating sinusoidal signals with a large number of samples per cycle. The phase of the generated sinusoids is continuous at the switching points, and the difference between any two adjacent generated frequencies is approximately constant. Simulation results are presented to verify the analysis and demonstrate the performance as measured in terms of total harmonic distortion. It is evident from the simulation results that the performance of the proposed oscillator is essentially the same as those of the previously reported oscillators with less hardware complexity.