A low-resistance self-aligned T-shaped gate for high-performancesub-0.1-μm CMOS |
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Authors: | Hisamoto D. Umeda K. Nakamura Y. Kimura S. |
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Affiliation: | Central Res. Lab., Hitachi Ltd., Tokyo; |
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Abstract: | This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability |
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