多电源混合电压SoC的全芯片ESD设计实例

SoC是含有微处理器、外围电路等的超大规模集成电路，具有器件特征尺寸小、复杂度高、面积大、数模混合等特点，SoC的ESD设计成为设计师面临的一个新的设计挑战。文章详细介绍了一个复杂的多电源、混合电压专用SoC芯片的全芯片ESD设计方案，并结合电路特点仔细分析了SoC芯片ESD设计的难点，提出了先工艺、再器件、再电路三个层次的分析思路，并将芯片ESD总体解决方案中的关键设计重点进行了逐一分析，最后给出了全芯片ESD防护架构的示意图。该SoC芯片基于0.35μm 2P4M Polycide混合信号CMOS工艺流片，采用文中提出的全芯片ESD防护架构，使该芯片的HBM ESD等级达到了4kV。

The Whole-chip ESD Design for Multi-power and Mixed-voltage SoC

SoC is a VLSI with microprocessor,peripheral circuits,and so on. SoC has some special features such as small device feature size,unusual complexity,large chip size and mixed-signals,etc.. All this leads chip designer to a new challenge in SoC ESD design. A whole-chip ESD protection solution of complicated multipower,mixed-voltage,application-specified SoC is proposed in this paper. Considering the chip specialties,detailed analyses for the ESD design difficulties of SoC are proposed in the paper. An analysi...