The multiple-processor PPS chip of the NON-VON 3 supercomputer

In this paper, we describe an experimental prototype VLSI chip that was designed to serve as the basis for a massively parallel supercomputer called NON-VON 3. The chip, which is implemented in 3-micron nMOS technology, contains eight 8-bit processing elements (PE's), each embodying 64 bytes of static RAM. Significant features of the design include: an unusually high processor density; a novel I/O switch that allows the machine to dynamically reconfigure to realize several logical communication topologies; logic supporting the pipelining of instructions, both within and among the individual PE's; a shared partial instruction decoder that reduces pinout and area, and a parallel self-testing, dynamically reconfigurable, fault-tolerant RAM that significantly increases both yield and reliability. The design and operation of the chip are discussed, along with its speed, area, and power dissipation characteristics.