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Architectures for language recognition
Authors:R.A. Evans  J.D. Morison
Affiliation:Royal Signals and Radar Establishment, St Andrew''s Road, Malvern, Worcestershire WRI4 3PS, United Kingdom
Abstract:Two distinct chip architectures for language recognition are presented. The first allows a recogniser for any regular expression to be constructed by simply assembling predefined cells into a linear array. The cells correspond to the symbols which can occur in a regular expression, and the appropriate cells are placed in a line in the same order as the expression. The recogniser is then correct by construction, and all inter-cell connections are made automatically. The second architecture can be programmed to recognise any LL(1) context-free language by loading it with the appropriate grammer rules. The grammar rules are embodied within an array of identical cells, which, in conjunction with a standard LIFO stack, form the recognition hardware.
Keywords:Language recognition  Syntactic pattern recognition  Syntax analysis  Parsers  Compilation  VLSI architectures
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