A low energy dual-mode adder |
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Authors: | Shmuel Wimer Amir Albeck Israel Koren |
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Affiliation: | 1. Bar-Ilan University, Engineering Faculty, Israel;2. Technion - Israel Institute of Technology, EE Faculty, Israel;3. University of Massachusetts, ECE Department, United States |
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Abstract: | VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. Adders in particular assume that addition must be completed within prescribed number of clock cycles, independently of the operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log2 n) bits. We present a novel dual-mode adder architecture that reduces the average energy consumption in up to 50%. In normal mode the adder targets the O(log2 n)-bit average worst-case carry propagation chains, while in extended mode it accommodates the less frequent O(n)-bit chain. We prove that minimum energy is achieved when the adder is designed for O(log2 n) carry propagation, and present a circuit implementation. Dual-mode adders enable voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time tradeoff obtained when incorporating such adders in ordinary microprocessor’s pipeline and other architectures is discussed. |
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