高速差分FIR滤波器的设计与实现

设计了一种对高速差分信号进行FIR滤波的滤波器结构。该结构采用FPGA内部RAM构成的异步FIFO乒乓接收高速输入数据，并以分频速率输出进行实时处理。FIR滤波器用VHDL语言和原理图相结合描述，并综合到Altera公司的Stratix系列芯片。综合结果表明．该设计能够接收高速差分信号，并能稳定工作在输入时钟的分频频率下。

Design and implementation of high-speed differential FIR filter

This paper designs a digital FIR filter architecture, which can be used to filter high-speed differential signals. The FIR architecture receives in pingpong mode high-speed signals using the asynchronous FIFOs formed by the RAMs in the FPGA, and outputs for real-time processing with divided frequency. The FIR architecture is written in VHDL and the block diagram, and is integrated into one of the Stratix series chips. The result shows that the designed architecture can receive high-speed differential signals and work at the divided frequency stably.