Characterizing wearout, breakdown and trap generation in thin silicon oxide

A model describing how wearout leads to breakdown in thin silicon oxides has been developed. During wearout defects or traps are generated inside the oxide and at the oxide interfaces. The signature of the trap generation is the permanent change in the transient current, in response to a voltage pulse, from an exponential decay to a 1/time decay. In oxides thinner than approximately 20 nm the dominant trap generation mechanism appears to be determined by the high fields across the oxides and not electron flow through the oxides. Locally higher current densities, flowing through the traps generated during wearout, lead to local breakdown. This model is critically dependent on the measurement of the properties of the traps generated inside the oxides during the wearout phase. The techniques for measurement of these traps and some of their properties have been described. The ability of this model to describe oxide charging, low-level leakages, transient currents, the role of asperities, polarity dependences, and the fluence, time, thickness, voltage and temperature dependences of oxide breakdown distributions has been discussed.