| 抗噪声和工艺参数浮动的高性能多输入多米诺或门设计 |
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| 引用本文： | 宫娜,汪金辉,郭宝增,王永清,曹晓兵,田秀丽. 抗噪声和工艺参数浮动的高性能多输入多米诺或门设计[J]. 半导体学报, 2009, 30(6): 065005-4 |
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| 作者姓名： | 宫娜 汪金辉 郭宝增 王永清 曹晓兵 田秀丽 |
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| 作者单位： | College;Electronic;Informational;Engineering;Hebei;University;VLSI;System;Laboratory;Beijing;Technology; |
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| 基金项目： | supported by the 2008 Scienceand Research Foundation of Hebei Education Department (No.2008308) |
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| 摘 要： | A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.
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| 关 键 词： | Domino 逻辑设计 性能 鲁棒性 CMOS技术 蒙特卡罗分析 低电源电压 技术使用 |
Robustness aware high performance high fan-in domino OR logic design |
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| Gong N,Wang Jinhui,Guo Baozeng,Wang Yongqing,Cao Xiaobing and Tian Xiuli. Robustness aware high performance high fan-in domino OR logic design[J]. Chinese Journal of Semiconductors, 2009, 30(6): 065005-4 |
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| Authors: | Gong N Wang Jinhui Guo Baozeng Wang Yongqing Cao Xiaobing Tian Xiuli |
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| Affiliation: | College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China;VLSI & System Laboratory, Beijing University of Technology, Beijing 100022, China;College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China;College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China;College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China;College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China |
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| Abstract: | A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively. Also, a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate. |
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| Keywords: | Domino OR robustness power consumption parameter variation |
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