| 功耗电流小于200nA的Al栅CMOSIDD失效分析 |
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| 引用本文： | 曹宏斌,赵桂茹.功耗电流小于200nA的Al栅CMOSIDD失效分析[J].半导体技术,1998,23(2):24-28. |
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| 作者姓名： | 曹宏斌 赵桂茹 |
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| 作者单位： | 西安微电子技术研究所 |
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| 摘 要： | 针对ＣＭＯＳ个别电路的静态功耗电流ＩＤＤ功率老化失效问题，根据ＣＭＯＳ的设计结构和工艺特点，本文从静电和栓锁的角度提出了几种失效模型并分析了ＩＤＤ几种失效机理。
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| 关 键 词： | 静态功耗电流 失效模型 CMOS IC 测试 |
Al Gate CMOS DD Lose Efficiency Analysis of Static Power Current Below 200nA |
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| Cao Hongbin,Zhao Guiru.Al Gate CMOS DD Lose Efficiency Analysis of Static Power Current Below 200nA[J].Semiconductor Technology,1998,23(2):24-28. |
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| Authors: | Cao Hongbin Zhao Guiru |
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| Abstract: | The static power current I DD power ageing lose efficiency of CMOS individual circuit is directed based on the structure and technology of the CMOS,from the point of view of electrostatic and latch up,a few lose efficiency models are presented and I DD several lose efficiency mechanism are analysed. |
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| Keywords: | Static power current Power ageing Lose efficiency model Microelectronics test pattern |
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