10bit 100MS/s混合型模数转换器

为了提高模数转换器的性能，将全并行模数转换器和逐次逼近型模数转换器相结合，设计了一种混合型模数转换器．为了进一步降低混合型模数转换器的功耗，提出了一种高位电容跳过与复用的开关策略．理论分析表明，相对于合并电容开关策略，提出的开关策略使电容阵列所需的电容总数减少了一半，电平切换功耗降低了81.22％．最后，基于中芯国际0.18μm工艺，对混合型模数转换器进行仿真．当采样频率为100MS／s、输入频率为48.14453125MHz的正弦波信号时，输出信号的无杂散波动态范围为75.879dB，有效位数为9.902bit，功耗为2.41mW，品质因数为25.19fJ／conversion-step．仿真结果表明，这种混合型模数转换器利用提出的开关策略能在功耗、速率和面积上实现很好的折中．

10bit 100MS/s Hybrid ADC

In order to improve the performance of the Analog-to-Digital Converter (ADC), a hybrid ADC has been designed which combines the Flash ADC and the Successive Approximation Register (SAR) ADC And a novel algorithm named Higher Capacitor Skipped or Reused (HCSR) is proposed to further improve the energy efficiency of the hybrid ADC. Theoretical analysis shows that the proposed switching scheme reduces the capacitor requirement by almost twofold and improves the average switching energy efficiency by 81.22％ compared with the Merged capacitor switching (MCS) algorithm. It is designed and simulated by SMIC 0.18μm technology The hybrid ADC achieves 75.879dB SFDR, 9.902bit ENOB, consumes 2.41mW and offers a good energy efficiency of 25.19fJ／conversion-step with the Nyquist input frequency at the sampling rate of 100MS／s. Simulation shows that the hybrid ADC which utilizes the proposed switching scheme achieves a perfect trade-off among speed, power, and area.