| 一种RapidIO IP核的设计与验证 |
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| 引用本文： | 蔡叶芳,田泽,李攀,何嘉文. 一种RapidIO IP核的设计与验证[J]. 计算机技术与发展, 2014, 0(10): 97-100 |
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| 作者姓名： | 蔡叶芳 田泽 李攀 何嘉文 |
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| 作者单位： | 中国航空计算技术研究所,陕西西安710119 |
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| 基金项目： | “十二五”微电子预研（51308010601）;总装2012预研基金（9140A08010712HK61095）;中国航空工业集团公司创新基金（2010BD63111） |
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| 摘 要： | RapidIO总线是第三代总线的代表，是处理器之间实现互联的最佳选择。但国内对于此技术的研究尚处于起步阶段，使用者也多以购买国外成熟IP为主。文中基于RapidIO V1.3协议，介绍了一种RapidIO总线的设计和实现方法，之后对其进行了全面的虚拟平台测试和FPGA平台测试。测试结果表明，该RapidIO总线符合RapidIO V1.3协议，且设计实现方式简单，复用性好，可以作为RapidIO接口方便地应用于FPGA和芯片设计中。
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| 关 键 词： | IP核设计 验证方法 |
Design and Implementation of a RapidIO IP Core |
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| CAI Ye-fang,TIAN Ze,LI Pan,HE Jia-wen. Design and Implementation of a RapidIO IP Core[J]. Computer Technology and Development, 2014, 0(10): 97-100 |
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| Authors: | CAI Ye-fang TIAN Ze LI Pan HE Jia-wen |
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| Affiliation: | ( Aeronautical Computing Technique Research Institute, Xi＇ an 710119, China) |
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| Abstract: | The RapidIO bus as one of the representatives of the third generation bus,is the best choice of the interconnection between pro-cessors. But in the domestic,the study of RapidIO bus is just begun,and the RapidIO IP is bought from outland mostly. Based on the Ra-pidIO V1. 3 protocol,describe a design and implementation method for the RapidIO bus,and has carried on the comprehensive test in vir-tual platform and FPGA platform. The simulation result shows that,this design meets the RapidIO V1. 3 protocol,and is simple to imple-ment,has good reusability,and can be easily used in the design of FPGA and chip as RapidIO interface. |
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| Keywords: | RapidIO RapidIO IP core design verification method |
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