Self-Checking Voter for High Speed TMR Systems

In this paper we address the problem of faults possibly affecting voters of TMR systems and making them provide incorrect majority data, thus making the adoption of the TMR technique useless. We consequently instantiate the need for self-checking voting schemes and propose a new CMOS self-checking voter that, compared to alternate self-checking solutions, features the advantage of being faster, while requiring comparable power consumption and a small increase in area overhead.José Manuel Cazeaux received his degree in Electronic Engineering from the University of Mar del Plata (Argentina) in 2002. In 2003 he was awarded a MADESS grant and joined the Electronics Department of the University of Bologna, where he is currently working towards his PhD in Electronic Engineering and Computer Science. His research interests are fault modeling, on-line testing and fault-tolerance techniques. He is a IEEE Student Member of the Computer Society.Daniele Rossi obtained the degree in Electronic Engineering from the University of Bologna in 2001. He is currently working towards his PhD in Electronic Engineering and Computer Science at the same University. His research interests include on-line testing and fault-tolerance techniques, with particular focus on coding techniques for fault tolerant and low power buses and for crosstalk effects minimization. He is a Member of the IEEE Computer Society.Cecilia Metra obtained the degree in Electronic Engineering and the PhD degree in Electronic Engineering and Computer Science from the University of Bologna (Italy). Currently, she is an Associate Professor in Electronics at the University of Bologna (Italy). From 1998 to 2001, she has also been Visiting Scholar at the University of Washington, Seattle (USA), while in 2002 she has been Visiting Faculty Consultant for Intel, Santa Clara (CA). She is General Co-Chair of “The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems” 2005 and Program Co-Chair of the “IEEE Int. On-Line Testing Symposium” 2005. She has been Program Co-Chair of the “IEEE Int. On-Line Testing Symposium”, 2004, 2003, Program Co-Chair/General Co-Chair of the “IEEE Int. On-Line Testing Workshop”, 2002, 2001 and “The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems”, 1998, 1999. She is/has been Member of the Technical Program Committee of several International Conferences. She is an Associate Editor for the IEEE Transactions on Computers and a Member of the Editorial Board of the Journal of Electronic Testing: Theory and Applications (Springer) and of the Microelectronics Journal (Elsevier Science). Her research interests are in the field of fault-tolerance, with particular emphasis on modular redundant systems, on-line testing techniques, error recovery and correction, fault analysis and modeling, concurrent diagnosis. She is a Member of the IEEE Computer Society.