| 基于改进4—2压缩结构的32位浮点乘法器设计 |
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| 引用本文： | 邵磊,李昆,张树丹 于宗光,徐睿.基于改进4—2压缩结构的32位浮点乘法器设计[J].微计算机信息,2007,23(3X):224-225,199. |
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| 作者姓名： | 邵磊 李昆 张树丹 于宗光 徐睿 |
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| 作者单位： | [1]江南大学信息工程学院,江苏无锡214036 [2]中国电子集团第58研究所,江苏无锡214035 |
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| 基金项目： | 本文获电子元器件可靠性物理及其应用技术国防科技重点实验室基金资（51433020105DZ6802） |
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| 摘 要： | 本文介绍一种用于高性能DSP的32位浮点乘法器设计,通过采用改进Booth编码的树状4-2压缩器结构,提高了速度,降低了功耗,该乘法器结构规则且适合于VLSI实现,单个周期内完成一次24位整数乘或者32位浮点乘。整个设计采用Verilog HDL语言结构级描述,用0.25um单元库进行逻辑综合.完成一次乘法运算时间为24.30ns.
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| 关 键 词： | 乘法器 4—2压缩器 浮点 |
| 文章编号： | 1008-0570（2007）03-3-0224-02 |
| 修稿时间： | 2007-02-032007-03-05 |
A design of 32-bit floating-point multipliers by using a structure of modified 4-2 column compression |
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| SHAO LEI LI KUN ZHANG SHUDAN YU ZHONGGUANG XU RUI.A design of 32-bit floating-point multipliers by using a structure of modified 4-2 column compression[J].Control & Automation,2007,23(3X):224-225,199. |
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| Authors: | SHAO LEI LI KUN ZHANG SHUDAN YU ZHONGGUANG XU RUI |
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| Abstract: | The paper explores a design for 32-bit floating-point multipliers ,which is used in high performances DSP chips. By using a structure of 4-2 column compression tree with the modified Booth encoding, the speed of the muhipliers is improved and the pow- er of the system is reduced. Furthermore, due to a more regular structure adopted, it is easy for VLSI reJization of the multipliers. The algorithm has been implemented in a 32-bit floating-point array multiplier, which performs single-cycle multiplication on 24-bit integer or 32-bit floating-point values. The whole design is described in Verilog DHL at structure level, and synthesized using the 0.25um standard cell library. It spends 24.30ns completing a 32-bit floating-point multiplication. |
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| Keywords: | multiplier 4-2 column compression floating-point |
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