一种全速率线性25Gb/s时钟数据恢复电路

面向高速光通信系统的应用,提出了一种全速率线性25Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25Gb/s数据眼图的差分电压峰峰值V_pp和抖动峰峰值分别为1.3V和2.93ps；输出25GHz时钟的差分电压峰峰值V_pp和抖动峰峰值分别为1V和2.51ps,相位噪声为-93.6dBc/Hz@1MHz。该芯片面积为1.18×1.07mm²,在1V的电源电压下功耗为51.36mW。

A Full-Rate Linear 25Gbps Clock and Data Recovery Circuit

In this paper, a full-rate linear 25Gbps clock and data recovery circuit (CDRC) is proposed for the application of high-speed optical communication systems. To achieve full-rate clock extraction and data recovery, CDRC employed a mixer-based linear phase detector and automatic frequency locking technique. No external reference clock was used in the design. Based on a 45nm CMOS process, the CDR circuit from the post-plate simulation results achieves that the peak-to-peak differential voltage V_pp and peak-to-peak jitter of the recovered 25Gbps data eye diagram are 1.3V and 2.93ps, respectively. The output 25GHz clock has a differential peak-to-peak voltage V_pp and peak-to-peak jitter of 1V and 2.51ps, respectively, with phase noise of -93.6dBc/Hz@1MHz. The chip has an area of 1.18×1.07mm² and consumes 51.36mW at a supply voltage of 1V.