基于符号补偿的RISC-V处理器乘法器优化

针对高性能RISC-V处理器乘法运算延迟过长的问题,改进了基本乘法器中的基4-Booth编码以及Wallace树型结构,提出了基于符号补偿的基4-Booth编码以及交替使用3-2压缩器和4-2压缩器的Wallace树型结构。基于符号补偿的基4-Booth编码减少了部分积的数量,降低了符号位进位翻转带来的功耗。改进的Wallace树型结构减少了部分积累加所花费的时钟周期,缩短了乘法器的关键路径,降低了乘法指令的执行延迟。利用VCS仿真验证了改进的乘法器功能正确性,通过板级测试评估了其性能。结果表明,本文的乘法器功能正确,相较于PicoRV32,执行整型乘法指令所花费的时钟周期缩短了88.2%。Dhrystone分数提高了71.7%,功耗降低了4.9%。

Optimization of RISC-V Processor Multiplier Based on Sign Compensation

In order to address the issue of excessive latency in multiplication operations of high-performance RISC-V processors, improvements have been made to the basic multiplier by modifying the base-4 Booth encoding and Wallace tree architecture. A novel approach based on signed compensation for base-4 Booth encoding and an alternation of 3-2 compressors and 4-2 compressors for the Wallace tree structure is proposed. The base-4 Booth encoding with signed compensation reduces the number of partial products and decreases the power consumption caused by sign bit carry flipping. The improved Wallace tree structure reduces the clock cycles required for partial product accumulation, shortening the critical path of the multiplier and reducing the execution delay of multiplication instructions. The functionality of the improved multiplier was verified using VCS simulation, and its performance was evaluated through board-level testing. The results demonstrate that the proposed multiplier functions correctly. Compared to the PicoRV32, the clock cycles required for executing integer multiplication instructions were reduced by 88.2%. The Dhrystone score increased by 71.7%, while power consumption decreased by 4.9%.