FinFET-based power-efficient,low leakage,and area-efficient DWT lifting architecture using power gating and reversible logic

For ultra-low-power applications, the computing components are smaller in size and consume less energy. In nonstationary signal analysis, the transformation plays an important role. Out of different transformation techniques, the most famous and dominant architecture is the discrete wavelet transform. The building block of the architecture should be optimized by all parameters. In this paper, the optimization was done on the power reduction and leakage current reduction. A new FinFET-based lifting-based wavelet architecture was proposed. Power gating and reversible logic methodology are proposed for the FinFET-based transform to reduce the dynamic power by about 30%. The proposed FinFET-based processing elements were utilized in the various blocks of the lifting-based DWT architecture. The implementation was done in 32-nm CMOS and FinFET technology. From the results, it has been investigated that the FinFET-based circuits are efficient when compared with CMOS technology. This is due to the second-order effects happening in CMOS circuits below 45 nm. The proposed design consumes less area and low leakage current and power when compared with the CMOS technology. Future trends of using multigate devices below 14 nm technology are presented finally.