Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage |
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| Authors: | Aditya Japa Manoj Kumar Majumder Subhendu K Sahoo Ramesh Vaddi |
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| Affiliation: | 1. Department of Electronics and Communication, DSPM International Institute of Information Technology, Naya Raipur, India;2. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Hyderabad, India;3. Department of Electronics and Communication, School of Engineering and Applied Sciences, SRM University, Guntur, India |
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| Abstract: | Tunnel field-effect transistor (TFET) exhibits significant p-i-n forward leakage with the increase in drain-to-source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low-power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p-i-n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished. |
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| Keywords: | hardware obfuscation p-i-n forward leakage true random number generators tunnel field effect transistor |
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