An efficient hardware realization of EMD for real-time signal processing applications

This paper presents a field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) based design for the real-time implementation of empirical mode decomposition (EMD) algorithm. Here, at the beginning, register-transfer-level (RTL) design of EMD algorithm is developed in the form of verilog-HDL code. Then, simulation-based testing of the RTL design is done. In this paper, two envelope computation methods are proposed: one using linear Bezier curve (LBC) and the other using cubic spline interpolation (CSI). For ASIC, the verilog-HDL code of EMD is synthesized using Genus tool of Cadence using SCL 180-nm technology library and Innovus tool of Cadence is used for the layout design. The core area of the proposed EMD ASIC is 1.16 mm² and can be operated at 62.5 MHz clock rate. The developed FPGA-based EMD architecture can be operated at 50 MHz clock rate and up to 50 MHz sampling rate. Here, an effort is also made to classify the normal and seizure/ictal electroencephalogram (EEG) signals, which are used as an input to EMD, with the help of a support vector machine (SVM). The classification accuracy obtained is above 99%, and here, MATLAB is used for feature calculation and classification purposes.