一种能有效降低Memory BIST功耗的方法

随着系统芯片(SoC)上存储器比重的日趋增加和Memory BIST(memory built-inself-test)的广泛应用,对较低测试功耗的嵌入式Memory BIST的设计要求越来越高,因为测试功耗一般为系统正常工作时的两倍多,而过高的功耗会烧毁电路和降低芯片成品率.通过采用按时钟域划分存储器组和串并结合的方法来降低Memory BIST的测试功耗.实验仿真结果表明,用该方法所得的最大功耗只有传统方法的1/14,可见该方法能有效降低测试时的能量损耗.

A Method of Reducing Power Consumption Effectively in Memory BIST

With the increasing proportion of memory in SoC(System on Chip) and the extensive application of Memory BIST(Built-In Self-Test), it is required more and more highly that the power consumption of embedded Memory BIST should be low when testing. Because testing power consumption of is much larger than that of normal system working. What’s more, to some extent, over high power consumption will ruin the circuits and reduce the yield of chip. This paper is mainly concentrated on reducing power consumption in Memory BIST design by partitioning many memories into groups according to clock domain and the mixture of serial and parallel methods. The simulation results show that, compared with the maximum power consumption generated by traditional measure, it is reduced 1/13 for that by the effective method. In a word, it is effective to reduce the power consumption.