| 基于EV10AQ190的高速ADC接口设计 |
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| 引用本文： | 肖汉波. 基于EV10AQ190的高速ADC接口设计[J]. 电子器件, 2015, 38(3): 569-575 |
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| 作者姓名： | 肖汉波 |
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| 作者单位： | 中国工程物理研究院电子工程研究所,四川 绵阳,621900 |
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| 基金项目： | “十二五”国防预研项目 |
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| 摘 要： | 针对E2V公司的高速ADC芯片EV10AQ190,提出了一种高速ADC接口电路设计方案。首先简要介绍了高速ADC芯片EV10AQ190技术特点,然后重点叙述了影响高速ADC接口电路性能的两大关键技术：FPGA片同步技术和多路ADC校正技术,最后给出了硬件调试及实验结果。实验结果表明,该高速ADC接口电路采样率可稳定工作在4GHz以上。这种方案已成功应用到某宽带雷达回波模拟系统的设计中。
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| 关 键 词： | 高速ADC EV10AQ190 片同步 多路校正 FPGA |
Design of Interface Circuit for High Speed ADC Based on EV10AQ190 |
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| XIAO Hanbo?. Design of Interface Circuit for High Speed ADC Based on EV10AQ190[J]. Journal of Electron Devices, 2015, 38(3): 569-575 |
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| Authors: | XIAO Hanbo? |
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| Affiliation: | XIAO Hanbo;Institute of Electronic Engineering,China Academy of Engineering Physics; |
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| Abstract: | Based on the application of EV10AQ190, a design scheme for high speed ADC interface circuit is presented. Firstly, the technical characteristics of EV10AQ190 are briefly introduced. Secondly, FPGA CHIPSYNC and multi-channel calibration are emphasized as two key technological points. Finally, the results of experiments and hardware debugging are shown, which have verified that this ADC interface circuit can be capable of working stably at a frequency higher than 4GHz. This solution has been utilized in the design of a wide-banded radar echo simulator. |
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| Keywords: | high speed ADC EV10AQ190 CHIPSYNC multi-channel calibration FPGA |
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